Defective memory cells occur when a semiconductor memory device is fabricated. A variety of techniques are used to repair the defective memory cells. Two repair techniques are: a redundancy repair technique for replacing defective memory cells by a row or column unit and an error correction code (hereinafter, referred to as “ECC”) for correcting errors of defective memory cells. ECC includes an on-chip ECC technique in which errors are corrected within a semiconductor memory device and an off-chip technique in which errors are corrected by an external controller for controlling the semiconductor memory device.
As a semiconductor memory device is scaled down, the number of defective memory cells increases sharply. A great deal of redundancy is required to replace defective memory cells using a conventional redundancy repair technique. This means that the size of a memory chip increases. A row redundancy circuit is formed of a plurality of row cell units (e.g., two or four word lines), or a column redundancy circuit is formed of a plurality of column cell units (e.g., four or eight bit lines). A problem of such redundancy circuits is that a lot of cells are unnecessarily used to repair a 1-bit defect. Also, a redundancy repair technique is not suitable to cope with reliability/quality problems caused after a fabrication process. In recent years, there has been research of on-chip and off-chip ECC techniques.